锁相环
充电泵
dBc公司
CMOS芯片
相位噪声
电子工程
计算机科学
电子线路
电气工程
噪音(视频)
节奏
电压
功率(物理)
集成电路设计
锁(火器)
工程类
物理
电容器
图像(数学)
机械工程
人工智能
量子力学
作者
Nashra Khalid,Ram Chandra Singh Chauhan
标识
DOI:10.1109/icccnt54827.2022.9984426
摘要
As the design of charge-pump (CP) circuits has progressed, some notable non-idealities, such as current mismatch, phase noise, and reference spur, have been noticed. One of the most important aspects of an effective CP design is lock-in time, yet achieving it always presents a challenge for usage in high-speed mobile communication. This work describes a straightforward drain switching-based charge-pump that uses minimal electricity. There is just an estimated 42.60 µm 2 of layout area. The suggested circuit is modelled using the CADENCE VIRTUOSO platform with 90nm CMOS technology working at 1.25GHz at 1.2V supply voltage. In comparison to the preconfigured circuits, the phase noise is stated to be -99.43 dBc/Hz @10MHz, and the current-mismatch is estimated to be 0.73% with an output range of 0-0.85V and lock-in time of 26ns. This qualifies it for PLL applications. To verify the effectiveness of a novel charge-pump circuit, Monte Carlo and process corner analysis are used.
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