Effect of lattice heating on the switching performance of a silicon‐gate all around dielectric window spaced‐multi‐channel MOSFET

Abstract In this article, analysis of heating effect for a range of thermal resistance () and different ambient temperatures on the DC parameters of the proposed Silicon‐Gate All Around Dielectric Window Spaced‐Multi‐channel (Si‐GAA‐DWS‐multi‐channel) MOSFET is carried out. The performance of the device is examined through 3D‐ATLAS TCAD simulator, by performing the numerical and electrothermal analysis. Due to cylindrical dimension, the nanowire FETs undergoes undesirable self/lattice‐heating. The lattice heating of the device is calculated with respect to various device parameters such as channel length, drain‐source voltage, thermal resistance, ambient temperature, on‐current , and off‐current . The proposed device parameter has been compared with the existing devices, mainly with Silicon‐Nanowire‐Dielectric Pocket Packed MOSFET (Si‐NW‐DPP FET) and Silicon‐Nanowire MOSFET (Si‐NW FET). The Si‐GAA‐DWS‐multi‐channel FET is found to be as the better device than the other two structures, as the leakage current of the device is improved by 1 and 2 decades, drain current increases by 1 and 1 decade, a minimum SS of 63.271 mV/dec and a minimum DIBL of 26.172 mV/V, respectively. The lesser the SS, the faster will be the device; hence the proposed structure can be considered as the finest prospect for VLSI/ULSI electronic chips.