Area-Selective Atomic Layer Deposition for Next-Generation Semiconductor Processing: Mechanisms of Selectivity Breakdown and Process Integration Strategies

As device miniaturization and three-dimensional integration progress, thin-film processes for semiconductor devices increasingly require atomic-level control not only of thickness and composition but also of growth location. Area-selective atomic layer deposition (AS-ALD) is a bottom-up process that exploits differences in surface reactivity between growth and non-growth areas to form thin films only at the intended locations. Because it enables self-aligned patterning and can reduce subsequent etching steps, AS-ALD has drawn attention as a candidate technology for next-generation semiconductor manufacturing. However, the high initial selectivity obtained on planar substrates is not always retained on real patterned or high-aspect-ratio structures. This review examines the process applicability of AS-ALD based on studies published through 2026, focusing on the selectivity window, the maximum selectively deposited thickness, the nucleation density in the non-growth area, and the preservation of pattern shape. Across the literature, the turning point of selectivity breakdown converges on the moment at which the first stable nucleus forms in the non-growth area. Residual surface defects and pinholes in the inhibition layer, together with precursor physisorption, penetration, thermal degradation, and lateral diffusion, all act to bring this transition forward in time. Molecular design strategies (inherent selectivity, self-assembled monolayers, small-molecule inhibitors, surface pretreatment, and combined precursor-inhibitor design) and process control strategies (inhibitor regeneration, ALD/ALE supercycles, and reactor control) are compared according to which stage of the nucleation pathway they intervene in. Pattern- or device-level demonstrations have accumulated for back-end-of-line interconnects and resistive random-access memory, whereas for DRAM, 3D NAND, and gate-all-around transistors most of the evidence remains at the level of material and process concepts. The performance of AS-ALD is difficult to judge from the initial selectivity value alone; a more direct criterion is whether the selectivity window-defined with respect to the target thickness and the tolerable defect level of the actual device structure-can be secured.