Using pattern analysis to improve wafer inspection flow

Circuit designs are becoming denser and more complex in advanced semiconductor process technologies. The foundry process windows are becoming smaller and smaller which increases sensitivity to wafer surface defects. These defects should be detected early to resolve the root causes and eventually help to improve the yield. Wafer defects are still often inspected manually while the defect counts can reach into the millions. It takes a long time to analyze and review the results while the identification of the root causes may be less accurate and buried in noise. In this paper, UMC advance research teams, in collaboration with the Cadence DFM team, utilized the Pegasus Computational Pattern Analytics (CPA) software to develop an enhanced inspection flow. This flow includes defect data preprocessing, classification, filtering, and reduction of huge data volumes to create visible and easy to review results. By finding more accurate root causes, we could reduce process develop time and finally improve wafer yields.