Ohmic contact engineering for SiC trench MOSFET: process optimization and underlying mechanism

Abstract Silicon carbide (SiC) trench metal–oxide–semiconductor field-effect transistors (MOSFETs) demonstrate significant potential for high-voltage and high-efficiency power conversion applications, owing to their high-power density and low switching losses. However, the quality and reliability of ohmic contacts critically affect the overall device performance, particularly the on-state resistance and threshold voltage stability. This work focuses on optimizing the ohmic contact process and elucidating the underlying mechanisms in SiC trench MOSFETs. To address the specific challenges posed by the trench architecture, we systematically investigate the effects of interface pretreatment, metal selection, deposition techniques and annealing conditions. Through characterization of scanning electron microscopy, focused ion beam, transmission electron microscopy and electrical measurement, the evolution of the contact interface microstructure and surface morphology was examined. Ultimately, high-performance trench-type SiC MOSFET devices featuring significantly reduced specific contact resistivity ( ρ c < 1 × 10 −5 Ω·cm 2 ) were successfully fabricated based on the optimized ohmic contact process. This study elucidates the influence mechanisms linking SiC ohmic contact process parameters, interface microstructure and electrical performance, providing crucial process solutions and a theoretical foundation for developing highly reliable trench-type SiC power devices.