High-performance optimization of SM4-GCM based on FPGA

SM4-GCM is an encryption algorithm with authentication function. The algorithm achieves the purpose of data security and information integrity. The SM4-GCM algorithm, implemented using traditional software methods, has low throughput and high resource consumption. In order to further improve the algorithm performance, this paper uses FPGA to optimize the SM4-GCM algorithm to achieve full-pipeline parallel acceleration. Firstly, the SM4 module is optimized using pipelining techniques. Then, the GHASH module is optimized using the Karatsuba algorithm and fast reduction. Finally, a loosely coupled architecture is used to connect various modules with asynchronous FIFOs, which improves the resource utilization and throughput of the FPGA circuit. The experimental results show that the throughput of the optimized SM4-GCM algorithm reaches 28.8 Gbps. It is better than other schemes, has a higher throughput, and meets the actual application requirements.