A Fast Settling 100dB OPAMP in 180nm CMOS Process with Compensation Based Optimisation

A two-stage gain-boosted OPAMP with 100dB DC gain, 807 MHz unity gain bandwidth (UGB) and rail to rail output swing in 180 nm digital CMOS process is presented. A compensation based optimisation methodology for fast settling response and closed loop stability is also described for this topology. Optimised settling response provides 0.001% settling time equal to 9.7 ns. This OPAMP is designed to be used as a current to voltage converter for 15-bit 100 MSamples/s DAC application. It could drive an off-chip capacitive load of 10 pF in parallel with a 500 ohm resistor and provides -94 dB THD at 100 KHz with a closed loop gain of 20 dB and 600 mV output swing.