About electron transport and spin control in semiconductor devices

As the scaling of CMOS-based technology displays signs of an imminent saturation, employing the second intrinsic electron characteristics – the electron spin – is attractive to further boost the performance of integrated circuits and to introduce new computational paradigms. A single electron spin forms a qubit and is suitable for quantum applications. In digital applications, the spin promises to offer an additional functionality to charge-based CMOS circuitry. Recently, spin injection into a semiconductor and spin manipulation by the gate voltage were successfully demonstrated providing a vision that devices using spin in addition to charge may appear in significant numbers on the market in the non-distant future. On the memory side, the nonvolatile CMOS-compatible spin-transfer torque (STT) and the spin–orbit torque (SOT) magnetoresistive random access memories (MRAMs) are already competing with flash memory and SRAM for embedded applications. A combination of nonvolatile elements with CMOS circuitry allows to shift the data processing into the nonvolatile segment, paving the way for a novel low power computational paradigm based on logic-in-memory and in-memory computing architectures. To model MRAM, we innovatively extend the spin and charge transport equations to multi-layered structures consisting of normal and ferromagnetic metal layers separated by tunnel barriers. We validate our approach by modeling the magnetization dynamics in ultra-scaled MRAM cells.