Compact Analog Chaotic Map Designs Using SOI Four-Gate Transistors

This work introduces three novel chaotic map circuits. Two of the map circuits use two $p$ -channel and one $n$ -channel silicon-on-insulator (SOI) four-gate transistor (G ⁴FET) while the third design uses two $n$ -channel and one $p$ -channel G ⁴FET. The multi-gate structure of G ⁴FET is leveraged to obtain four independent bifurcation parameters in the chaotic map with a simple three-transistor design. A chaotic oscillator design is proposed using this discrete-time chaotic map circuit, and the chaotic behavior is evaluated using bifurcation plot, Lyapunov exponent (LE), Correlation coefficient, Shannon entropy, and Stability analysis. The application of this multi-parameter chaotic oscillator is presented in a chaos-based reconfigurable logic gate, and the significant expansion of parameter design space compared to existing single-gate transistor-based maps is also demonstrated. Finally, a simple extension scheme for developing multi-dimensional robust chaotic map with even larger parameter space is presented and verified with specific instances of 2-D and 3-D maps.