计算机科学
CMOS芯片
模拟设备
模拟电子学
模拟信号处理
炸薯条
人工神经网络
电子工程
堆栈(抽象数据类型)
模拟计算机
功率(物理)
模拟乘法器
电气工程
模拟信号
电子线路
计算机硬件
工程类
人工智能
数字信号处理
电信
物理
量子力学
程序设计语言
作者
Kazuki Tsuda,Kazuma Furutani,Yuto Yakubo,Hiromichi Godo,Yoshinori Ando,Atsutake Kosuge,Toru Nakura,Shunpei Yamazaki
标识
DOI:10.1109/jeds.2024.3439712
摘要
We prototyped a true analog current computing multilayer neural network (NN) chip, where multiple analog in-memory computing (AiMC) circuit blocks are connected to each other via simple analog non-linear operation circuits. The true analog current computing is achieved with the invention of an analog current rectified linear unit (ReLU) circuit of a three-stage current mirror. With the prototyped NN chip, we demonstrated that the true analog computing (1) achieves process variation compensation utilizing current driving, (2) eliminates digital-analog or analog-digital data conversion between NNs, and (3) realizes low power inference, not only in multiply-accumulate (MAC) but in ReLU operation. Through classification of Mixed National Institute of Standards and Technology dataset, the chip exhibits a low energy of 1.1 nJ/classification and an accuracy of 91.6%, achieves weight retention of five hours, much longer than dynamic random access memory, and enables 68% power reduction compared with serially connected two single-layer NN chips with analog-digital converters and digital-analog converters in between. Although periodic refresh from an external storage class memory is necessary for applications that require continuous operation exceeding five hours, our AiMC capable of MAC and non-linear operations with low power is effective in applications such as edge artificial intelligence terminals with limited power sources.
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