(Invited) Influence of Ga 2 O 3 /Al 2 O 3 Interface on Characteristics of Ga 2 O 3 Capacitors

Various β-Ga 2 O 3 -based power devices have been widely investigated because β-Ga 2 O 3 has a large bandgap of ~4.9 eV and high breakdown electric field of 8 MVcm -1 [1-3]. It is well understood to be important to reduce the number of electrical defects at the Ga 2 O 3 /dielectric interface for n-β-Ga 2 O 3 /dielectric/metal capacitor. However. it was unclear which process in the fabrication of β-Ga 2 O 3 capacitors caused these electrical defects. For example, surface cleaning of the β-Ga 2 O 3 substrate, an Al 2 O 3 film deposition as a dielectric by the atomic layer deposition (ALD) method, and high-temperature annealing (HTA) are considered. On the other hand, for GaN power device, we reported that Ga 2 O 3 interfacial layer was generally grown at GaN/SiO 2 interface and affected to electrical properties. And we recently proposed dummy SiO 2 technique ( d-SiO 2 ) to improve the quality of the Ga 2 O 3 layer on the GaN surface [4]. In this study, we tried to modify the Ga 2 O 3 /Al 2 O 3 interface using the surface cleaning of β-Ga 2 O 3 substrate, HTA at various annealing temperatures in O 2 ambient, and d-SiO 2 . We also discuss about influence of Ga 2 O 3 /Al 2 O 3 interface on characteristic including physical and electrical properties for Ga 2 O 3 capacitors. In the Ga 2 O 3 surface cleaning process, the characteristics of β-Ga 2 O 3 /Al 2 O 3 /Pt capacitors fabricated by using with and without BHF treatment after Aceton and SPM treatment were firstly compared. No difference was observed in the surface roughness of the Ga 2 O 3 substrate. Positive flatband voltage (V fb ) shift increased with increasing the BHF treatment time under positive bias stress (PBS). Based on these experimental data, the capacitor was generally fabricated using the standard process including the SPM treatment and maximum fabrication temperature at 300 °C (Standard). Next, after annealing β-Ga 2 O 3 substrates at 800-1000 °C in O 2 , the Al 2 O 3 capacitors were also prepared (HTA-capacitor). The large V fb hysteresis of the HTA-capacitors increased from 1.6 to 1.9V at V-V fb = 4.0V as annealing temperature increased while the Standard capacitor maintained V fb hysteresis of 0.73V. It is thought that the number of trapped/detrapped electrons increased. Finally, characteristics of the capacitors fabricated by d-SiO 2 were examined. After cleaning β-Ga 2 O 3 substrate using SPM solution, a dummy SiO 2 (5 nm) layer was deposited on β-Ga 2 O 3 via plasma-enhanced ALD at 300 °C. Post annealing was carried out at 800-1000 °C in O 2 . Here, we confirmed that Ga diffused into SiO 2 layer regardless of annealing temperature by SIMS analysis, indicating that Ga-O decompose to Ga atoms at Ga 2 O 3 surface. A dummy SiO 2 layer was removed using HF solution. Next, a 10-nm-thick Al 2 O 3 dielectric was deposited on modified-Ga 2 O 3 substrate via ALD at 300 °C, Pt gate electrode and Ti/Pt ohmic contact were formed. Finally, Post metallization annealing was performed at 300 °C (d-capacitor). The V fb hysteresis of the d-capacitors significantly reduced to 0.4V at V-V fb = 4.0V regardless of annealing temperature while the V fb hysteresis of the Standard capacitor exhibited 0.73V, indicating that the modified Ga 2 O 3 surface was able to decrease the number of trapped/detrapped electrons. To study reliability, the bias V-Vfb was applied to 2.0V under PBS. The V fb shifted toward positive direction as the stress time increased from 0 to 300s, indicating the presence of some electron trapping sites at β-Ga 2 O 3 /Al 2 O 3 interface of the capacitors. The d-capacitors exhibited significantly smaller V fb shift value compared to the Standard and HTA-capacitors. We conclude that a stable Ga 2 O 3 surface was formed by d-SiO 2 and could be obtained a small V fb hysteresis and superior reliability under PBS for β-Ga 2 O 3 /Al 2 O 3 capacitor. This research was supported by the Ministry of Education, Culture, Sports, Science and Technology, Japan (MEXT), through its "Creation of Innovative Core Technology for Power Electronics" Program Grant Number JPJ009777 and ARIM (JPMXP1223NM5088). Reference [1] M. Higashiwaki et al., Appl. Phys. Lett. 100, 0135