The behaviour of very high current density power MOSFETs

This paper presents a new description of the operation of a power MOSFET which is aimed at assisting in the design of devices which operate at high current densities. We analyse the charge balances within a power MOSFET (DMOS or UMOS) and show how these conspire to dictate the operation of the device. We report on the manufacture of a UMOS device with 0.8 /spl mu/m cells with 0.4 /spl mu/m trench widths=540/spl times/10/sup 6/ cells/in/sup 2/.