Negative resistance, capacitance in Mn/SiO2/p-Si MOS structure

Abstract In this work is that we have manufactured a new structure that had not been studied by researchers before. This structure is Mn/SiO 2 /Si was synthesised by liquid phase epitaxy (LPE) as a metal-oxide- semiconductor (MOS) and can be used as a tunneling diode; demonstrated from I–V measurement and negative resistance. The structure and its characterization were examined by scanning electron microscope, XRD diffraction, C-V and I–V measurements. We studied the temperature, voltage dependence of dielectric and electrical parameters of the fabricated Mn/SiO 2 /P-Si MOS device. I–V measurements for this structure display diode tunnel behavior with negative resistance. Parameters such as series resistance (Rs), permittivity ( ε ′), dielectric loss ( ε ″), a tangent of the dielectric loss factor (tan δ ), real and imaginary parts of electrical modulus (M′ and M″) and ac conductivity were examined in a temperature range of 303–393 K and frequency range (10 Hz–20 MHz) under 1 Vrms applied voltage along with dc bias range of (−2.0–2.0 V). We found that thermal reordering of the interface is a reason for a continuous density distribution of interface states with homogenous relaxation time, which in turn induced a higher sensitivity to both C and G/w response with electric field frequency. The device showed negative values for capacitance (C), dielectric loss ( ε ″), and dielectric loss tangent (tan δ ) at all temperatures.