A 90 to 170V scalable P-LDMOS with accompanied high voltage PJFET
作者
John Ellis-Monaghan,Yun Shi,Santosh Kumar Sharma,N. Feilchenfeld,Ted Letavic,Rick Phelps,Crystal Hedges,D. Cook,J. Dunn
标识
DOI：10.1109/ispsd.2012.6229040
摘要
A novel JFET redesign of a laterally scaled P-LDMOS device is presented. The P-LDMOS device has excellent Rsp as it is scaled from 90V to 170V operation. This P-LDMOS design is modified to produce a 100V PJFET with good turn-off characteristics and a relatively low Vpinch of 3-7V.
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(2025-6-4)
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