Noise and Error Analysis and Optimization of a CMOS Latched Comparator

In a high speed latched comparator the minimum amount of differential voltage at the input can be detected correctly at the output of the comparator if it does not get affected by the noises and errors generated inside the comparator. To improve the performance of the latched comparator, all the noises and errors should be minimized. In this paper, an attempt has been made to reduce the noises and errors generated within the latched comparator by introducing extra circuit elements. The noise and error optimized comparator shows an improvement in the effective resolution from 7.46-bit to 8.3-bit.