A 127 nA Quiescent Current Capacitorless NMOS LDO with Fast-Transient Response

In this paper, a fully-on-chip, NMOS low dropout (LDO) regulator with nA quiescent current is proposed. This work combines the dynamic and adaptive current biasing techniques to improve the transient response while maintaining the quiescent current at nA level. The proposed LDO is designed in a 0.18-μm CMOS process and consumes 127 nA quiescent current with 100 mV dropout voltage for generating an output voltage of 800 mV. Furthermore, the output voltage undershoots 215 mv and takes less than 400 ns settling time when the load current steps from 1 μA to 10 mA in 500 ns.