Analysis and characterization of layout dependent effect for advance FinFET circuit design

Layout dependent effects (LDEs) will cause electrical variation of FinFET circuits and even lead to manufacture failure in advanced technology stage. In this paper, we study the stress-correlated LDEs in FinFET device and found that LDEs cause 17.8% of maximum saturate current shift and 4.6% of maximum threshold voltage shift. We designed different test patterns and analyzed the variation of Current-Voltage (I-V) characteristics generated by LDEs on 14 nm FinFET technology. By simulating electrical performance of FinFET devices under different LDE-related parameters, the correlations between LDE-related parameters and device variation trend are obtained, which will be able to provide guidance for circuit layout optimization. The relevant characteristics are incorporated into I-V characteristic analysis methodology, providing circuit designers the guides in determining the geometric and electrical parameters of devices. Further, generation principles and physical mechanisms of LDEs were studied in this paper.