A 43-fJ/Conv, 1-GS/s Energy-Efficient Charge-Steering Comparator with Floating-Inverter-Based Preamplifier in 40nm CMOS

This paper presents an energy efficient charge steering comparator with floating inverter-based preamplifier. The proposed comparator employs dynamic biasing operation in both the preamplifier and the comparator. This approach allows it to outperform the conventional strong-arm latch in terms of both energy efficiency and speed, making it particularly suitable for low-power applications. The architecture was designed, thoroughly simulated, and post-layout optimized using a 40nm CMOS technology. The proposed comparator achieves an energy efficiency of 43fJ per conversion with a supply voltage of 0.9V while operating at 1GHz.