加速
数据流
计算机科学
卷积神经网络
并行计算
卷积(计算机科学)
计算机工程
工作量
比例(比率)
库达
瓶颈
频道(广播)
加速度
计算机体系结构
人工神经网络
人工智能
嵌入式系统
电信
物理
量子力学
经典力学
操作系统
作者
Yishuo Meng,Siwei Xiang,Jianfei Wang,Jia Hou,Chen Yang
出处
期刊:IEEE Transactions on Circuits and Systems Ii-express Briefs
[Institute of Electrical and Electronics Engineers]
日期:2024-01-29
卷期号:71 (7): 3473-3477
被引量:1
标识
DOI:10.1109/tcsii.2024.3359263
摘要
The customization of accelerators for sparse convolutional neural networks (SCNN) has been demonstrated to be a promising approach to enhance the computational efficiency of CNNs. However, current sparse-based works always employ reduced-scale convolutional engines (CEs), resulting in limited performance compared to previous dense-based accelerators. It is found that the deployment of large-scale CEs to sparse-based works encounters three challenges: inadequate utilization of CEs, unstable workload of CEs and complex interconnections between CEs and accumulators. Therefore, in this paper, first, a novel position-first dataflow is proposed to streamline the interconnections between the CEs and accumulators of the architecture. In addition, an input channel merging method is devised to improve the inadequate utilization and unstable workload of CEs. With the assistance of the above two schemes, a sparse-based acceleration architecture with an expanded-scale convolution array is designed and implemented on Xilinx VCU118 platform, achieving a runtime frequency of 300MHz. The comparison results demonstrate that compared with current sparse-based works, our proposed architecture can achieve 1.10×-3.95× speedup on actual performance and 1.10×-2.52× speedup on DSP efficiency, respectively, when VGG16 is applied.
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