乘法函数
维数(图论)
算法
数学
离散数学
数学分析
组合数学
作者
Julián G. Fernández,Natalia Seoane,Enrique Comesaña,Antonio J. García‐Loureiro
标识
DOI:10.1109/jeds.2022.3214928
摘要
The impact of different variability sources on the transistor performance increases as devices are scaled-down, being the metal grain granularity (MGG) and the line edge roughness (LER) some of the major contributors to this increase. Variability studies require the simulation of large samples of different device configurations to have statistical significance, increasing the computational cost. A novel Pelgrom-based predictive (PBP) model that estimates the impact of MGG and LER through the study of the threshold voltage standard deviation $\left(\sigma V_{T h}\right)$ , is proposed. This technique is computationally efficient since once the threshold voltage mismatch is calculated, $\sigma V_{T h}$ can be predicted for different gate lengths $\left(L_{g}\right)$ , cross-sections, and intrinsic variability parameters, without further simulations. The validity of the PBP model is demonstrated for three state-of-the-art architectures (FinFETs, nanowire FETs, and nanosheet FETs) with different $L_{g}$ , cross-sections, and drain biases $\left(V_{D}\right)$ . The relative errors between the predicted and simulated data are lower than 10%, in the 92% of the cases.
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