Neutron induced single event effects on near-memory computing architecture AI chips

冯·诺依曼建筑 事件(粒子物理) 散裂中子源 中子 计算机科学 炸薯条 建筑 单事件翻转 软错误 计算机硬件 嵌入式系统 并行计算 散裂 物理 静态随机存取存储器 核物理学 操作系统 工程类 电子工程 天体物理学 电信 艺术 视觉艺术
作者
Weitao Yang,Zhi-Liang Hu,He Huan,Li-Hua Mo,Xiao-Hong Zhao,Wu-Qing Song,Tian-Cheng Yi,Tianjiao Liang,Chaohui He,Yonghong Li,Bin Wang,Longsheng Wu,Huan Liu,Guang Shi,School of Microelectronics, Xidian University, Xi’an 710071, China,School of Nuclear Science and Technology, Xi’an Jiaotong University, Xi’an 710049, China,Spallation Neutron Source Science Center, Dongguan 523803, China,Aviation Engineering Institute, Air Force Engineering University, Xi’an 710000, China,School of Aerospace Science and Technology, Xidian University, Xi’an 710071, China
出处
期刊:Chinese Physics [Acta Physica Sinica, Chinese Physical Society and Institute of Physics, Chinese Academy of Sciences]
卷期号:73 (13): 138502-138502 被引量:1
标识
DOI:10.7498/aps.73.20240430
摘要

For the near-memory computing architecture AI chip manufactured by using 16 nm FinFET technology, atmospheric neutron single event effect irradiation tests are conducted for the first time in China by using the atmospheric neutron irradiation spectrometer (ANIS) at the China Spallation Neutron Source. During the irradiation, the YOLOV5 algorithm neural network running on the AI chip is used for real-time detection of target objects, including mice, keyboard, and luggage. The purpose of the test is to investigate the new single event effect that may occur on near-memory computing architecture AI chip. Finally, at an accumulated neutron fluence of 1.51×10<sup>10</sup> n·cm<sup>–2</sup> (above 1 MeV), a total of 35 soft errors are detected in 5 categories. Particularly noteworthy is the observation of a new finding, where both computing and memory units experience single event effects simultaneously, which is different from the traditional von Neumann architecture chips. Based on the single event effects that occur simultaneously in these two units, combined with Monte Carlo simulation, a preliminary estimation is made of the physical layout distance between the computing unit and the memory unit on the chip. Furthermore, suggestions are proposed to simultaneously reduce the risk of single event effect in multi cells. This study provides valuable reference and insights for further exploring the single event effects in non-traditional von Neumann architecture chips.
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