EUV full-chip curvilinear mask options for logic via and metal patterning

With the adoption of multi-beam mask writing (MBMW) technology, there is a strong drive to realize the maximum lithographic process window entitlement which can be obtained with curvilinear masks, including both SRAFs and main features. Inverse Lithography Technology (ILT) has always featured prominently in planning for such masks, as it can produce the ideal curvilinear patterns which represent the best possible solution. The runtime for ILT, however, remains too slow for full-chip logic manufacturing and this paper will review multiple alternative approaches which endeavor to produce similar output masks but with significantly faster runtime. Results will be shown for 3nm-node via and metal examples where full ILT, hybrid ILT & dense curvilinear OPC, hybrid curvilinear SRAF & dense curvilinear OPC, and machine learning approaches will be assessed for runtime and a variety of lithographic metrics. Overall, all solutions are shown to be considerably faster than full ILT, ranging between 4x (for hybrid ILT SRAF) to <100X improved runtime performance. Lithographic capability is characterized in terms of distributions of edge placement errors (EPE), PV Bands, and ILS/NILS. There are some minor differences between the various options, but given the pronounced runtime advantages over ILT, all are compelling options, delivering lithographic PW enablement close to the ideal ILT solution. For the model-based DNN, and Monotonic Machine Learning (MML) approaches, we will discuss the approach, challenges, and advantages associated with robust training to ensure the broadest possible pattern coverage.