A critique of length and bias dependent constraints for 1T-DRAM operation through RFET

Abstract Capacitorless dynamic memory (one transistor dynamic random access memory (1T-DRAM)) operation in a reconfigurable field effect transistor (RFET) is critically governed by different lengths associated with the architecture. These lengths consisting of ungated region ( L UG ), control gate ( L CG ), polarity gate ( L PG ), storage region length ( L S ), and total length ( L T ) can be sensitive to the fabrication process, and hence, critical for 1T-DRAM. This work presents an insightful critique of the above mentioned lengths for realising optimal 1T-DRAM performance. It is shown that RFET with highest values of L S / L T and L CG / L T shows good short channel immunity but does not necessarily ensure enhanced 1T-DRAM metrics. Results indicate that for a fixed L T , retention time can vary over a wide range (550 ms to 8.7 s) depending on the values of L S / L T and L CG / L T , and hence, appropriate optimization is imperative. The work contributes towards better understanding and optimizing L CG / L T to ensure improved 1T-DRAM metrics in terms of enhanced retention (>64 ms), acceptable sense margin (>6 µ A µ m −1 ), current ratio (>10 4 ) with low values of read (2 ns) and write (1 ns) time to further extend multi-functional facets of nanoscale RFETs for memory applications. In addition, the effect of traps, process sensitivity, reduced number of voltage levels, and disturbance caused by shared word line (WL)/bit line (BL) are also analysed in this work. Results indicate that state ‘0’ of the cell sharing BL with the selected cell is strongly affected by BL disturbance. WL disturbance primarily impacts state ‘1’ of the cell sharing WL with selected cell (only for write 1 and read operations).