Process Optimization and Yield Improvement for Erase Failure in Embedded Flash Memory

This work is aimed at the yield improvement with root cause definition on erase failure inside flash cell by novel process optimization in embedded flash memory device. It is analysis that the root cause the very gross erase failure was mainly due to the abnormal short circuit between bit lines (BL) and floating gate (FG) ploy inside flash matrix cell. Furthermore, it turned out that coupling ratio of FG and control gate (CG) which impacts programing and erasing of flash cell is one of big modulators to flash performance. To tackle these problems, a new approach to eliminate the short circuit by simply process optimization without increasing cost. More importantly, the coupling ratio of FG/CG inside flash cell was carried out so as to increase read current window, leading to the successful performance improvement. Our efforts demonstrate that the erase defect has been eliminated and the flash yield has reached 95.6% through process and structure optimizations.