Transition-Region Co-Optimization for Enhanced dV/dt Ruggedness in 4H-SiC MOSFETs

Under high-speed switching conditions, silicon car bide (SiC) metal–oxide-semiconductor field-effect transistors (MOSFETs) are susceptible to reliability failures induced by high dV/dt stress, which has emerged as a critical bottleneck limiting their high-frequency and high-efficiency applications. This article presents a systematic investigation of the failure behavior and underlying physical mechanisms of 1200 V 4H SiC MOSFETs under high dV/dt conditions. Transient electric field concentration across the thin gate oxide in the transition region is identified as the primary trigger of dV/dt-induced failure, based on double-pulse testing combined with EMMI, FIB, and SEM failure analyses. Further TCAD transient simulations reveal that both an excessive thin-gate-oxide length and dynamic incomplete-ionization effects contribute to severe transient gate oxide electric-field intensification during fast voltage ramping. Based on these insights, a co-optimization strategy centered on electric-field redistribution is proposed and experimentally validated by shortening the thin-gate-oxide length and reducing the surface doping concentration in the transition region. The optimized device can operate reliably at dV/dt exceeding 330 V/ns, with no failure observed even under the extreme condition of Rg = 0 Ω, representing more than a threefold improvement over the original device. Furthermore, continuous-pulse stress tests demonstrate stable gate leakage current after 2.5 × 106 high-speed switching cycles under dV/dt stress above 300 V/ns, indicating no observable gate-oxide degradation. Large-scale statistical measurements on 1200 V devices confirm that key static parameters, including threshold voltage, on-resistance, and breakdown voltage, remain unchanged, while HTRB testing at 175°C for 1000 h verifies that the proposed optimization does not compromise long-term static reliability.