收发机
数字信号处理
计算机科学
电子工程
光电子学
材料科学
计算机硬件
工程类
CMOS芯片
作者
J. Q. Wang,A. Tan,Ashwin K. Iyer,A. Fan,A. Farhoodfar,Basel Alnabulsi,B. Smith,C. Loi,Cherng-Rong Ho,Dragos Cartina,J. Riani,J. Casanova,K. Raviprakash,Lokanath Patra,L. Wang,M. Bachu,Sagar Ray,Shin Wei Chong,S. Dallaire,T.V. Nguyen
标识
DOI:10.1109/isscc49657.2024.10454275
摘要
The application of artificial intelligence (AI) and machine learning (ML) in network switching and cloud computing require 200Gb/s per wavelength to minimize the number of optical ports and enable a cost-effective solution to meet the higher throughput demands. In turn, this data rate requires aggressive performance metrics such as high transceiver bandwidth (BW) that is 2 times higher than the previous generation, low circuit noise, and low clock jitter. In addition, lower power consumption per bit is needed to fit into the optical module power envelop which is specified by multi-source agreements (MSA) such as OSFP-XD. This work presents a low-power and high-performance 200Gb/s transceiver used for optical direct-detect applications. Figure 7.1.1 shows an example 800Gb/s optical module where the line side is made up of 4 lanes, with each lane consisting of a 200Gb/s transmitter (TX) and 200Gb/s receiver (RX). To leverage the power and area benefits in technology scaling, a digital to analog converter (DAC) based TX and an analog to digital converter (ADC) based RX running at 106GS/s are used. In the TX, an FIR filter pre-compensates for the channel BW limitation, and digital pre-distortion adjusts PAM-4 inner levels for optimal SNR performance. In the RX, the sampled ADC signal is equalized by an FFE and a reflection canceller, and depending on channel conditions, a DFE and maximum likelihood sequence detector (MLSD) can be enabled for higher SNR performance.
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