Electrothermal Reliability Analysis of Electromigration in 3-D TSV-RDL Interconnects

In three-dimension integrated circuits (3-D ICs), Through Silicon Via (TSV) enables vertical connectivity between stacked chips or interposers and has become one of the main interconnect structures. With the increasing number of inputs and outputs (I/Os) and decreasing interconnection spacing, electromigration (EM)-induced electrical interconnection failures have raised concerns in the field of microelectronics. This paper investigated the EM reliability and failure mechanisms of the TSV and Redistributed layer (RDL) interconnects in the presence of electro-thermal effects. The relationships between resistance and migration mechanisms are studied through a combination of simulation and experimentation. Accelerated life testing is employed to monitor the resistance evolution, while the Atomic Flux Divergence (AFD) method is utilized to pinpoint the initial location of the migrations, with a higher occurrence observed on RDL lines. Ultimately, this research provides a methodology to assess the reliability of the mechanical, thermal, and electrical properties of the 3-D interconnects. Competitive circuit designs are proposed for the comprehensive impact of electro-thermal effects, aiming to minimize atomic migration, particularly in high-density circuits.