覆盖
计算机科学
半导体器件制造
过程(计算)
GSM演进的增强数据速率
公制(单位)
忠诚
还原(数学)
机器学习
光学接近校正
人工智能
计算机工程
可靠性工程
工程类
电气工程
程序设计语言
薄脆饼
几何学
操作系统
电信
数学
运营管理
作者
Anh T. Ngo,Bappaditya Dey,Sandip Halder,Stefan De Gendt,Changhai Wang
标识
DOI:10.1109/tsm.2022.3217326
摘要
As the semiconductor manufacturing process is moving towards the 3 nm node, there is a crucial need to reduce the edge placement error (EPE) to ensure proper functioning of the integrated circuit (IC) devices. EPE is the most important metric that quantify the fidelity of fabricated patterns in multi-patterning processes, and it is the combination of overlay errors and critical dimension (CD) errors. Recent advances in machine learning have enabled many new possibilities to improve the performance and efficiency of EPE optimization techniques. In this paper, we conducted a survey of recent research work that applied machine learning/ deep learning techniques for the purposes of enhancing virtual overlay metrology, reducing overlay error, and improving mask optimization methods for EPE reduction. Thorough discussions about the objectives, datasets, input features, models, key findings, and limitations are provided. In general, the results of the review work show a great potential of machine learning techniques in aiding the improvement of EPE in the field of semiconductor manufacturing.
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