DTCO of Nanosheet and Forksheet Architectures: Exploring Dielectric Walls, Contacting Schemes, and Active Regions for Optimized RO Performance

Using an advanced Design Technology Co-Optimization (DTCO) framework, we benchmark gate-all-around Nanosheet (GAA-NS) and Forksheet (FS) architectures at multiple metal pitches (Mx), active widths ($\mathrm{W}_{\mathrm{Ns}}$), and contacting schemes, viz. buried power rail (BPR) and backside power rail (BS-PR) with backside contact (BSC). Interestingly, we find that while at larger cell height (CH), FS perform better than NS, at smaller CH it is the reverse. From a performance perspective, while BSC does not provide any benefit for a wrapped-around contact baseline, it does provide an active width advantage (2 nm extra $\mathrm{W}_{\mathrm{NS}}$). We also introduce a novel GAA-FS device for enhanced gate control and investigate asymmetric-FS for optimized performance at different Mx.