Ultrashallow Junction (USJ) Fabrication by Advanced Ion Implantation Processes

For advanced CMOS device process, a preamorphization implant (PAI) procedure had been carried on source and drain (SD) lightly doped source and drain (LDD), heavily doped source and drain (HDD), and contact implants before an ultralow energy (ULE) beamline (BL)-based implant to depress the channeling effect for lower OFF-current and short channel effect (SCE). One-step plasma doping (PLAD) was utilized to replace this two-step BL implant process for the pMOS device because PLAD has an in situ real-time controllability for less channeling effect. The PLAD using B ₂ H ₆ gas with ULE high dose regime was utilized for this application. It significantly reduces cost and increases throughput because this one low-cost PLAD module eliminates PAI BL implant. The pMOS devices also exhibit significant performance improvements, including ~30% lower contact resistances ( R _CS ), similar threshold voltage ( V _T ) and subthreshold voltage (SV _T ) characteristics, and ~8% higher drive currents (I _DS ) without degrading OFF-current (I _OFF ).