Development of 2.5D high density device on large ultra-thin active interposer

In the recent years, the industry is moving towards finer, higher density interconnections and better electrical performance from the die to the substrate. The 3D stack assembly using through silicon via (TSVs) has been emerging as a good solution by using heterogeneous technologies. By stacking the ICs heterogeneously, TSV technologies can allow for faster electrical performance with little signal propagation time delay, consumes less power and smaller foot prints. In addition, the TSV technology also removes the using of substrate at finer pitch and integrate high power performance interconnects functions for chip-to-chip communication [1]. The work presented in this paper highlights the assembly challenges in the attachment process of the chip-on-chip substrate package onto the large $150\mu \mathrm{m}$ pitch Via-Last TSVs interposer at $40\mu \mathrm{m}$ thickness. The top level design consists of an FPGA (28nm, 12.65 m x 12.34 mm size, Arria V programmable SoC), two IO chips (65nm, 4mmx 4mm, Split IO and ESD) flip chip attached to a 130nm active through silicon interposer with dimension 22.8 mm x 16.4 mm. In summary, the method of handling such a thin large active interposer at 40um poses many challenges in the TSV assembly. A different assembly approach is required to ensure minimum silicon interposer warpage and allows for good SnAg solder formation and wetting for both the FPGA die and the 65nm dies during reflow process. Detailed underfill process optimization needs to be studied to achieve no voids in the Fine pitch interconnect assembly on large active silicon interposer. The assembled ATSI package is able to pass with good electrical continuity results for 3 different reliability tests.