n-Type Si solar cells with passivating electron contact: Identifying sources for efficiency limitations by wafer thickness and resistivity variation

薄脆饼 电阻率和电导率 共发射极 材料科学 兴奋剂 太阳能电池 工作职能 光电子学 能量转换效率 纳米技术 图层(电子) 电气工程 工程类
作者
Armin Richter,Jan Benick,Frank Feldmann,Andreas Fell,Martin Hermle,Stefan W. Glunz
出处
期刊:Solar Energy Materials and Solar Cells [Elsevier BV]
卷期号:173: 96-105 被引量:560
标识
DOI:10.1016/j.solmat.2017.05.042
摘要

In this work, the efficiency of n-type silicon solar cells with a front side boron-doped emitter and a full-area tunnel oxide passivating electron contact was studied experimentally as a function of wafer thickness W and resistivity ρb. Conversion efficiencies in the range of 25.0% have been obtained for all variations studied in this work, which cover 150 µm to 400 µm thick wafers and resistivities from 1 Ω cm to 10 Ω cm. We present a detailed cell analysis based on three-dimensional full-area device simulations using the solar cell simulation tool Quokka. We show that the experimental variation of the wafer thickness and resistivity at device level in combination with a detailed simulation study allows the identification of recombination induced loss mechanisms. This is possible because different recombination mechanisms can have a very specific influence on the I-V parameters as a function of W and ρb. In fact, we identified Shockley-Read-Hall recombination in the c-Si bulk as the source of a significant FF reduction in case of high resistivity Si. This shows that cells made of high resistivity Si are very sensitive to even a weak lifetime limitation in the c-Si bulk. Applying low resistivity 1 Ω cm n-type Si in combination with optimized fabrication processes, we achieved confirmed efficiency values of 25.7%, with a VOC of 725 mV, a FF of 83.3% and a JSC of 42.5 mA/cm2. This represents the highest efficiency reported for both-sides contacted c-Si solar cells. Thus, the results presented in this work demonstrate not only the potential of the cell structure, but also that a variation of the wafer thickness and resistivity at device level can provide deep insights into the cell performance.
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