Understanding the limits of ultrathin SiO2 and SiON gate dielectrics for sub-50 nm CMOS

In spite of its many attributes such as nativity to silicon, low interfacial defect density, high melting point, large energy gap, high resistivity, and good dielectric strength, SiO2 suffers from one disadvantage, low dielectric constant (K=3.9). Thus, ultrathin SiO2 gate dielectric layers are required to generate the high capacitance and drive current required of sub-50 nm transistors. The silicon industry roadmap dictates 4 nm SiO2 gate dielectrics for 0.25 μm technology today, and calls for <1 nm equivalent SiO2 thickness for 0.05 μm technology in 2012. SiO2 layers in this thickness range may suffer from boron penetration, reduced drive current, reliability degradation, and high gate leakage current. We will argue that none of these problems are limitations for thicknesses greater than about 1.3 nm. Below that thickness, the fundamental problems of high tunneling current and reduced current drive will prevent further scaling, unless alternate gate dielectrics are introduced.