Capacitor-Coupled Offset-Canceled DRAM Sense Amplifier With Ultralow Offset Voltage and Hidden Cancelation Time

The sense amplifier (SA) is a critical component for DRAM to detect the small voltage difference between bit-lines and amplify it to rail-to-rail output. As DRAM technology scales down, threshold voltage mismatches between transistors become more pronounced, which increases SA offset voltage and prolongs sensing time (tSEN). This work proposes a capacitor-coupled sense amplifier (UH-COSA) with ultralow offset voltage and hidden cancellation time. The UH-COSA reduces the tSEN by hiding the offset-cancellation operation within the charge sharing operation. UH-COSA introduces a pre-sensing stage, and enables positive feedback to improve the sensing margin. UH-COSA use one capacitor to store the voltage difference between pre-charge voltage VEQ and one inverter trip-point, and one capacitor to store the voltage difference of two inverter trip-point voltages. Post-layout simulation results show the UH-COSA having high PVT stability. Even at a low supply voltage of 0.75 V and large bit-line load capacitance of 160 fF, the sensing yield can reach 99.85%. Compared with other capacitor-coupled SAs, UH-COSA shows advantages of shortest sensing time, and smallest standard deviation of offset voltage.