缩放比例
接触电阻
单层
晶体管
材料科学
频道(广播)
光电子学
纳米技术
电气工程
图层(电子)
工程类
数学
几何学
电压
作者
Wen-Chia Wu,Terry Y.T. Hung,D. Mahaveer Sathaiya,Dongxu Fan,Goutham Arutchelvan,Chen-Feng Hsu,Sheng‐Kai Su,Ang Sheng Chou,Edward Chen,Weisheng Li,Zhihao Yu,Hao Qiu,Ying-Mei Yang,Kuang-I Lin,Yun-Yang Shen,Wen‐Hao Chang,San Lin Liew,Vincent Hou,Jin Cai,Chung-Cheng Wu
出处
期刊:
日期:2023-06-11
卷期号:: 1-2
被引量:14
标识
DOI:10.23919/vlsitechnologyandcir57934.2023.10185408
摘要
Two-dimensional transition metal dichalcogenides (2D TMDs) are expected to enable extremely scaled logic transistors for their ultrathin body and superior electrostatic control, i.e. gate length scaling. Aggressive scaling requires also contact length scaling. Here we demonstrate contact length scaling with low contact resistance of sub-100 Ω-μm (best data in TLM) through optimized surface preparation and semimetal/metal stack. Monolayer-MoS 2 channel transistors have the same driving current at contact length down to 30 nm. A calibrated TCAD model which captured device trends is used to extrapolate to ~250 Ω-μm at sub-15nm contact length per nanosheet of MoS 2 .
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