Design and Analysis of the Morris–Lecar Spiking Neuron in Efficient Analog Implementation

We propose the design and analysis of the Morris-Lecar spiking neuron in optimized analog implementation from a methodical standpoint to frame the neuron design within a theoretical context targeting the design of efficient solutions for the low-complexity analog implementation of Spiking Neural Networks (SNNs). In the proposed neuron CMOS circuit, the most chip area-consumer elements that are generally a leakage resistor and state capacitors have been crossed off while the neuron excitation stimuli is adjusted through an on-chip single transistor. Furthermore, the proposed analysis is potentially investigated to enhance the reliability and robustness of the analog system by embracing the effects of intrinsic random manufacturing process variations. The study is developed based on a 45nm standard CMOS technology for low power applications.