Wafer to wafer bonding to increase memory density

Fulfilling huge memory chip demand in strong growth applications like Internet of Things, mobile telephones and datacenters requires memory manufacturers to constantly evolve the manufacturing process of 3D NAND flash memories. Wafer to wafer hybrid bonding has been introduced in new generation memories to overcome scaling limit and eliminating several 3D NAND manufacturing challenges. Wafer to wafer bonding in memories involves joining a NAND array wafer to the logic wafer. The wafer-to-wafer hybrid memory design was introduced to continue Moore's law in the third dimension. Copper metals from the two wafers are joined together to form one component. This hybrid bond between two individual wafers permits the manufacturer to produce denser and smaller dies with high-speed data transfer rate. Benefits of wafer-to-wafer bonding could attract manufacturers to adopt this design to continue miniaturization of NAND memory components. Wafer to wafer hybrid bonded NAND chips is compared to conventional 3D NAND memories to reveal density and cost benefits of the novel design. Relentless advancements in 3D NAND designs, together with the emergence of hybrid architectures have enabled continuous NAND memory bit cost reduction while improving the memory characteristics.