Interface Engineering for Steep Slope Cryogenic MOSFETs

In this work, we study experimentally the impact of different gate dielectric stacks on the subthreshold behavior of cryogenic MOSFETs. While in room temperature devices, silicon nitride deteriorates the off-state of MOSFETs it turns out that at cryogenic temperatures an appropriately thin, grown silicon nitride layer in combination with a high-k gate dielectric counteracts the saturation of the inverse subthreshold slope and inflection phenomena. As a result, steep slope cryogenic MOSFETs with strongly improved subthreshold behavior are demonstrated.