Design and implementation of Silicon Doped FerroGate Stacking JL-VTFET in MIC SEPIC Convertor

This paper introduces a Ferro technique in the junctionless vertical tunnel field effect transistor in which the ferroelectric property in the [Formula: see text] is developed with the help of Silicon doping in it. The incorporation of the ferroelectric oxide stacking with [Formula: see text] results in low sub-threshold slope and high trans-conductance which is highly suitable for sensing of small voltage and converting it into strong drain current. The introduction of the high k-dielectric material with [Formula: see text] also leads to small lattice mismatch so that the losses can be reduced. The device shows ON current in the order of (2.62 × 10[Formula: see text]A/[Formula: see text]m) and the ratio of the ON to OFF drain current is noted as (of 2.031 × 10[Formula: see text]). Moreover, the device exhibits sub-threshold slope 35mV/dec and the ratio of trans-conductance to drain current (gm/[Formula: see text]) in the range of 150–350 V[Formula: see text]. Then the design structure is used to develop the circuit of multiple input converters (MIC) because the device shows high conversion rate (trans-conductance). For the converter, State-space analysis is used for the modeling of converter which was further followed with the design of converters’ energy storing apparatus with its voltage gain formulation. Interaction analysis is used to create a decentralized controller. The controllers’ robustness is tested using parametric uncertainty. A 175-watt experimental archetype with 36 volt and 24-volt sources is developed in the lab. The digital controller was implemented using the processor. The efficacy of controllers for regulating sources and loads has been verified. The controller’s strength is ensured by the satisfactory correlation between simulation and investigational results. For the result outcome one can validate Silicon Doped Ferro Gate Stacking JL-VTFET results for low power applications.