Advanced processing control for wafer-to-wafer hybrid bonding

3D heterogeneous integration is an evolving segment in integrated circuit development and advanced packaging to drive More than Moore (MtM) chip scaling. Heterogeneous integration allows IC manufacturers to stack and integrate more silicon devices in a single package, increasing the transistor density and product performance. Product designers seek higher bandwidth, increased power, improved signal integrity, more flexible designs (mix/match different chip functions, sizes, and technology nodes), and lower overall costs. The 3D heterogeneous integration roadmap shows a decrease in the bonding bumps/pads pitch to a sub-micrometer level, enabling a higher bump I/O density. Key process development activity is occurring in the wafer-to-wafer (W2W) bonding process to reduce interconnect pitch to small values. In the W2W process, a wafer bonder is used to align and bond two whole wafers. To successfully unite these two bond surfaces with a very small pitch, tight control of the bond pad alignment is required to ensure the copper pads line up properly before being bonded, driving an increased need for overlay metrology precision and die-bonder control. The bonded wafers are subsequently cut up into stacked chips using a dicing process and then undergo testing and further packaging. Advanced processing control (APC) for W2W hybrid bonding is an important factor in fulfilling the target on-product overlay (OPO) via litho inputs, in-plane distortion (IPD), overlay (OVL) and bonder correction knobs. This work will evaluate the various aspects impacting OPO, including the pre and post-bonding error budget.