Fundamental understanding of quantum confinement effect on gate oxide reliability for gate-all around field-effect transistor

Gate oxide reliability has become a significant concern for emerging technology nodes, particularly as transistors continue to scale down. Quantum confinement effects in nano-scaled devices complicate the trapping dynamics near the interface. Although these behaviors can be modeled using density-functional theory (DFT) and Marcus theory, a more efficient method is essential for characterizing critical reliability issues at the nano-device level. This paper presents a pioneering numerical study that employs a Bohm potential and Marcus theory, examining carrier concentration decay near the channel/oxide interface to evaluate the charge-trapping process using density-gradient coupled Poisson equations. This approach incorporates vital quantum corrections to classical studies. Key physics-based parameters are initially derived from DFT calculations and subsequently calibrated against experimental data. Our findings indicate that charge trap rates decrease with carrier density at the interface, ultimately affecting the device's threshold voltage shift.