Low sheet resistance buried metal bit line realized by high-temperature metal CVD process in vertical channel transistor array

Abstract With the continuous evolution of dynamic random access memory (DRAM) devices, there is a growing demand for increased storage density per unit area. In this work, we aim to create a high-density array of vertical channel transistors using advanced DRAM process technology. A thickness of SiO 2 ( X +3 nm) was determined for the protective layer, which shows the best-protecting effect. We employed CVD to grow thin Ti films on the array’s bottom. To reduce the resistance of the buried bit line (BBL), we formed a high-quality metal silicide using a thermal annealing process combined with self-align technology. Nanoprobe measurement results show an average resistance of approximately 60 Ω of the bit line of each cell transistor, where the low series resistance can improve device performance. Our work involved optimizing the protective layers and achieving high-performance BBLs, paving the way for the development of high-density DRAMs.