Parameter Extraction of Extended Floating Gate Field Effect Transistors (EGFETs): Estimating the Threshold Voltage, Series Resistance, and Mobility Degradation From I-V Measurements

等效串联电阻 降级(电信) 系列(地层学) 阈值电压 材料科学 晶体管 光电子学 萃取(化学) 电子工程 电气工程 电压 工程类 化学 色谱法 生物 古生物学
作者
Yunsoo Park,Santosh Pandey
出处
期刊:Social Science Research Network [Social Science Electronic Publishing]
被引量:1
标识
DOI:10.2139/ssrn.4514281
摘要

Extended Floating Gate Field Effect Transistors (EGFETs) are CMOS-compatible floating gate devices capable of detecting charges on their sensing area by the relative shifts in current-voltage (I-V) characteristics. The I-V shifts are generally computed by measuring the EGFET parameters in the strong inversion region of operation. This could lead to errors in estimating the device sensitivity because the simple I-V model ignores the mobility degradation and series resistance effects in EGFETs. Our goal is to model these parasitic effects and present methods to extract the key device parameters. We derive an analytical I-V model for EGFETs in the linear region of transistor operation, accounting for both the mobility degradation and series resistance effects. Based on the analytical model, three methods are presented to estimate the key parameters, namely the threshold voltage, series resistance, surface roughness parameter, low-field mobility, and effective mobility from the I-V characteristics, gate transconductance, and drain conductance. The peak transconductance method is used as a benchmark for comparing the extracted threshold voltages. Silicon-based EGFET devices are fabricated, and their I-V characteristics are measured with deionized water and three polyelectrolytes. From the I-V data, the parameter extraction methods are used to compute the values of the key parameters, and the suitability of each method is discussed. The gate transconductance methods show good agreement between the values for the key parameters, while the drain transconductance method gives lower values of the key parameters. There is scope to improve the presented methods by incorporating the effects of substrate bias and asymmetric series resistance for new extended-gate device architectures, including solution-based organic field-effect transistors.

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