A 200MS/s, 77dB-DR Two-Stage SAR ADC with Asynchronous Pipelining and Reference Snubbers

This paper presents a low-noise ADC for low-power, low-latency signal acquisition chains. It features asynchronous pipelining to improve backend precision while minimizing the conversion latency to 8 ns, independent of sample rate. Domain-crossing reference snubbers address settling and ringing limitations of the precision references, for the sub-ADCs and the floating-inverter residue amplifier. Implemented in 40 nm CMOS, the proposed design achieves a 71.1 dB peak SNDR and 77 dB DR at 200 MS/s, consuming 5.8 mW. It advances the speed of state-of-art low-noise SAR ADCs by $2.5 \times$ and delivers a best-in-class noise-level and DR with a 179.4 dB $\text{FoM}_{\mathrm{S},\text{DR}}$.