1700 V Charge-Balance-Assisted SiC MOSFETs for Improved Short-Circuit Capability

In this article, a 1700V charge-balance-assisted SiC MOSFET with an orthogonal layout was proposed, and three devices with different pillar widths were designed. Its short-circuit (SC) robustness was investigated at both 25°C and 175°C. Experimental results revealed that all the proposed devices not only exhibited improved SC capability but also achieved a reduction in on-resistance (R_dson) without compromising blocking capability. Notably, the device with a N-pillar width of 1.2 μm and a P-pillar width of 1.8 μm achieved a 20.1% reduction in R_dson, a 70% increase in short-circuit withstand time (SCWT) to 5.1 μs, and a 16.1% increase in short-circuit energy (E_sc) to 2.52J under 1000V bus voltage at 25°C. The enhanced SC capability resulted from the structural optimization, which led to lower junction temperatures and slower temperature rise. In addition, the observed performance among various pillar designs was related to the lateral depletion. With such a practical device design approach, the charge-balance-assisted SiC MOSFETs demonstrated better tradeoff between Rdson and SC robustness.