Warpage Prediction Improvements for Thin Package-on-Package Architectures

Abstract The Package-on-Package (PoP) architecture gained widescale popularity for its relatively lower power consumption and smaller form-factor compared to traditional flip-chip (FC) packages and wafer level FC packages. This was because it effectively shortened the interconnection distance between processor chip and low power double data rate (LPDDR) memory. While the extent of CTE mismatch increased in this architecture, posing significant warpage driven yield loss, researchers have successfully developed finite elements-based simulation methods to predict warpage accurately. Some of the regular Finite Element warpage modeling assumptions made for a traditional Flip Chip Package-on-Package (FC PoP) architectures fail when it comes to thinner PoP architectures. The significantly reduced overall package height for thinner PoP architecture has made its warpage behavior extremely sensitive to the extent of copper content in the package. This high sensitivity is what makes finite elements modeling based warpage prediction challenging. The limited body of published work in this area does point to use of process-based approach for warpage prediction. While promising results and methods have been reported, this methodology is found to be quite cumbersome. Also, the accuracy of the warpage prediction at Room Temperature (RT) and High Temperature (HT) is found to be extremely reliant on one having full access to the detailed process steps which often changes from OSAT vendor to OSAT vendor, and many times deemed confidential, making this approach even more challenging. This paper demonstrates a modified version of the traditional End-of-Line (EoL) Finite Elements based simulation approach to predict warpage shape and magnitude for an already highly sensitive thin PoP architectures. A detailed methodology has been described, alongside step-by-step comparison of warpage prediction improvements from the conventional method to the modified version.