Simulation of different structured gate-all-around FETs for 2nm node

Abstract This paper compares different types of Gate All Around (GAA) FET structures using TCAD simulation, including Lateral Nanosheet, Lateral Nanowire, Vertical Nanosheet, and Vertical Nanowire. The increase in electrostatic control and reduced short channel effects are key benefits to adopting GAAFET structures to meet scaling requirements for next generation process nodes. To understand channel geometry impacts on performance, the channel effective width (W eff ) is swept around the projected dimensions, including ratio of height and width parameters. The performance is evaluated using the key device metrics such as on-state current (I on ), off-state current (I off ), and threshold voltage (V t ) for transfer characteristics, and drain-induced barrier lowering (DIBL), subthreshold slope (SS), and gate induced drain leakage (GIDL) for short-channel effects. It is observed that thinner channel geometries, as often seen implemented in Nanosheet structures, have major benefits across SCE and I off metrics compared to more symmetrically square shaped channels. Additionally, stacking channels as a means to increase W eff appears to be an attractive option for increasing performance without significant increase in SCEs observed. For bulk technology the ratio between height and width of a Nanosheet structure can be optimized to reduce parasitic channel influence, so that optimal I on /I off ratio is achieved.