A novel algorithmic Data-Collision SDRAM-based TCAM architecture on FPGA

Ternary Content-Addressable Memory (TCAM) is one of the most effective methods for high-speed data searching in networking infrastructure. Despite the excellent performance and large look-up table, application-specific integrated- circuit-based TCAMs cost massive power supply and are challenging to configure. Field-Programmable Gate Arrays (FPGAs) have become the alternative solution for integrating TCAM due to their minimal power consumption and reconfigurability. Methods using on-chip registers, BRAMs, or LUTRAMs to implement large-size TCAM suffer excessive resource consumption. Researchers introduced DDR-SDRAM-based CAM to provide high-performance and economic packet inspections to overcome such issues; however, they only support binary look-up. This paper presents a novel algorithmic Data-Collision TCAM architecture on FPGA for SDRAM compatibility. The proposed SDRAM- based TCAM supports ternary value look-up function for practical Ethernet packet processing. The architecture outperforms conventional TCAMs regarding BRAMs, logics consumption, and look-up table sizes. The proposed architecture is the first SDRAM-based TCAM on FPGA with a 128Mbyte look-up table.