Heterogeneous Tapped Delay-Line Time-to-Digital Converter on Artix-7 FPGA

Time-to-Digital Converters (TDCs) implemented on Field-Programmable Gate Arrays (FPGAs) have become increasingly prevalent across a wide range of scientific and engineering disciplines, such as high-energy physics experiments, autonomous driving, robotic navigation, and medical imaging, owing to their cost-effectiveness, high precision, and rapid development cycles. This article presents a 3-tap heterogeneous tapped delay-line (TDL) architecture for a FPGA-based TDC that can be employed for multi-channel time-of-flight measurement. The TDC desgin is based on the open-source jTDC, featuring single-cycle dead time and multi-channel expansion capabilities, with an original precision of 30 ps. Combined with jTDC’s dynamic caching mechanism using dual-page memory, this work employs a dual-cycle encoding and calibration. The proposed architecture has been implemented on a Xilinx Artix-7 FPGA. According to the experimental results, an optimal 3-tap heterogeneous TDL architecture achieves a resolution of 23.220 ps and a typical precision of 17.520 ps, whereas an optimal 4-tap heterogeneous TDL architecture demonstrates a resolution of 17.530 ps and a typical precision of 17.213 ps. A comparison with recently published state-of-the-art FPGA-based TDCs is provided at the end of the article.