A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicers and PRTS Checker

This article presents a 40-Gb/s (25.6 GBaud) quarter-rate receiver utilizing three-level pulse amplitude modulation (PAM). The continuous-time linear equalizer (CTLE) with a passive high-pass filter provides a boosting gain of 13 dB at 12.8 GHz. A two-tap data decision feedback equalizer (DFE) and a one-tap edge DFE are included. The phase detector (PD) logic directly controls the digitally controlled oscillator (DCO) to reduce the loop latency. This receiver is fabricated by a 28-nm CMOS process and its area is 0.12 mm $^{2}$ . By using a pseudorandom ternary sequence (PRTS) of 3 $^{7} - 1$ , this 40-Gb/s receiver compensates the channel loss up to 23-dB loss with a bit error rate (BER) $<$ 10 $^{-12}$ . The total power consumption of this receiver is 90 mW at 40-Gb/s, which achieves an FoM of 98 fJ/bit/dB.